Transposed Form of Folded Fir Filter

The designing method of folded finite-impulse response (FIR) filter on pipelined array based multiplier arrays is presented in this paper. The design is considered at the bit-level of the pipelined multiplier array and internal delays are fully exploited in order to reduce power consumption and hardware complexity, transposed FIR filter forms is considered. The proposed schemes are compared as to the aspect of hardware complexity with a straightforward implementation of a folded FIR filter based on the pipelined Wallace Tree multiplier. The comparison reveals that the proposed schemes requirement is very less hardware. Finally, the efficient implementation of folded FIR filter circuits is presented when constraints in area, clock frequency and power consumption. Keywords—Filter, Folded, Transposed, FIR, Adder, Multiplier, Pipeline, Array. .